1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. In particular, the present invention relates to a high-speed miniaturized field effect transistor including silicided source and drain electrodes, and a method of manufacturing such a transistor.
2. Background Art
In order to further achieve a high-speed and highly-functional semiconductor circuits, demand for the miniaturization and the larger scale integration of individual semiconductor devices is continually growing. However, shrinking the dimensions of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), i.e., main components of such semiconductor circuits induces various kinds of problems.
For example, as the channel length (i.e., the length of a gate electrode) of a MOSFET is decreased, the threshold voltage thereof decreases accordingly (short-channel effect). Due to high sensitivity of the threshold voltage of the small size MOSFETs on the channel length, even a slight variation of channel length (i.e., the gate length) leads to undesirable change of a threshold voltage from the value intended at the time of the designing of the semiconductor circuit and eventually impairs the entire function of the circuit. It entails that, since the value of the threshold voltage strongly depends on the size of the gate electrode, a slight process variation may not be tolerated to obtain an intended electronic function and extremely tight control of the process conditions is necessitated to achieve successful manufacturing. This is very inconvenient for the manufacturing of a semiconductor circuit, such as a DRAM (Dynamic Random Access Memory), which requires a large number of highly uniform elements.
Such a short channel effect is caused by the distortion of the electric fields originated from the source and drain electrodes of the MOSFET reaching the central area of the channel region as the channel length decreases. Such an influence of the electric fields of the source and drain electrodes can be avoided by bringing up the pn junction positions of the source and drain regions closer to the surface of the semiconductor device (i.e., to make the pn junction portions shallower). However, shallower pn junctions leads to an increase in the electric resistance of the source and drain electrodes, which hinders the high-speed transmission of electric signals.
In order to solve such a problem and to reduce the electric resistance of the source and drain electrodes, upper parts of the source and drain electrodes are made to react with a certain metal (silicidation). Metal elements such as Co, Ti, Ni, etc., are used to form a silicide (i.e., chemical compound between Si and the metal). Among them, Co and Ni are the most suitable for the use in miniaturized LSIs, since no increase in electrical resistance (thin line effect) is observed even when the silicides thereof are formed on very thin silicon lines. However, at the time of the silicidation reaction or during a heat treatment performed thereafter, a part of metal atoms drifts away from the reaction surface or silicide/silicon interface and migrates deep into the silicon substrate, where the source and drain regions are formed. Thus, when the pn junctions are made shallow, the diffused metal atoms would easily reach the junction depth, thereby causing a severe junction leakage current.
Actually, in the case of Co, a rapid thermal annealing at a temperature of 800° C. for 30 seconds is required in order to form a low-resistance phase of silicide, CoSi2. However, since the diffusion of Co atoms is extremely fast, the Co atoms reach 150 nm in depth even with the aforementioned short heat treatment. FIG. 18 shows the junction leakage current as a function of n+/p junction depth after 35 nm-thick CoSi2 formation. For comparison, the junction leakage currents of reference samples without silicide formation are also plotted. Clearly, additional leakage generation is already evident at the depth of 150 nm, which is far deeper than the depth of the silicide layer. This is caused by the diffusion of Co atoms into the substrate.
When Ni is used, the leakage current can be reduced due to lower reaction temperature and smaller silicon consumption of Ni silicidation reaction as compared to the case of using Co. Also, for Ni silicidation, formation of an iridium intermediate layer between a silicon substrate and a nickel silicide layer is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 2002-367929, in order to decrease the junction leakage current further. The technique claims that the formation of the iridium intermediate layer increases the phase transition temperature from NiSi to NiSi2, resulting in leakage suppression even at a temperature of 850° C.
However, without such a special treatment, a rapid diffusion of metal atoms is unavoidable at the interface between a metal and silicon, as described above. The metal atoms deeply diffused into the silicon substrate form gap states in the silicon forbidden band. Naturally, the gap states formed at the source and drain junctions generate leakage currents.
When leakage currents flow through the source and drain junctions, the performance of the device is degraded. In the case of a storage element such as a DRAM, the information stored therein is erased, and the primary function of the semiconductor device is lost.
In order to solve the aforementioned problems, an elevated source drain method has been utilized. In this method, semiconductor layers are selectively and additionally formed (for example, silicon is grown) on surface portions of a semiconductor substrate where source and drain electrodes are to be formed. Because the surfaces of this additionally formed semiconductor layers are higher than the original semiconductor surface (i.e., the surface where a channel is to be formed), pn junction depths of the source and drain are shallow relative to the original semiconductor surface, but deep relative to the newly formed surfaces, securing the enough depth of the electrode while suppressing the short channel effects. Such a selective silicon growth can be achieved by using an epitaxial growth method.
In this method, however, the depth of the pn junction of the source and drain must be precisely set to the same level as the original semiconductor surface or kept slightly deeper than this level. If the junction depth does not reach the channel surface, the drivability of the MOSFET is severely compromised. On the other hand, when the junction depth is considerably deeper than the channel surface, a short-channel effect becomes a problem.
However, the epitaxial growth technique is very sensitive to the surface conditions where the selective growth is to be performed. For example, the thickness of the silicon layer to be grown strongly depends on the surface states (such as roughness, asperity, impurity, and residual damages) and the crystal structure of the substrate. Furthermore, the quality of the layer (i.e., the presence of crystal) also depends on the surface condition as well. Thus, due to the influence of a natural oxide layer on the substrate or residual damage caused at the time of the gate electrode processing, the thickness and the quality of the silicon layer formed on the individual source and drain regions may change significantly. When the thickness of the additional silicon layer is not uniform, it is impossible to adjust the pn junction depth of all devices precisely to the original semiconductor substrate surface (i.e., the surface where a channel is formed). This is because, since the impurities used to form the source and drain are implanted through the surface of the additionally formed silicon layer, the junction depth need to be targeted in reference to the distance from this newly formed surfaces. Non-uniform thickness means variable positions of the original semiconductor surface relative to the additionally formed silicon surfaces, thus no way of accurate ajustment.
In addition, when the quality of the additionally formed silicon layer are not uniform, it becomes difficult to accurately position the pn junction at the intended location. Since the speed of the diffusion of impurities is modified (transient enhanced diffusion) depending on the quality of the layer, if the quality of the silicon layer are not uniform, even when a predetermined thermal diffusion of impurities is applied in order to position the junction portions at the channel surface, the diffusion would proceed in an unexpected manner for each regions, resulting in non-uniform junction depths.
The same applies to the diffusion of metal atoms at the time of silicidation. Even with the additional silicon layer, when the thickness or quality of the layer is not uniform, the metal atoms can easily penetrate the junction depth at a position of thin thickness or poor quality, thereby causing a junction leakage current.
Furthermore, the speed of the diffusion of metal atoms itself is very high. Accordingly, the thickness of the additionally formed silicon layer should be very thick to block the diffusion amounting to 150 nm. However, for the aforementioned reasons, it is practically impossible to achieve a uniform and selective silicon growth of 150 nm-thickness. Moreover, the additional layer of 150 nm-thickness would have almost the same height as the gate electrode. Accordingly, with such a thickness, it becomes difficult to secure the electric isolation between the gate and the source and drain electrodes when silicidation reaction is made to proceed on these electrodes at a time (self-aligned silicidation, or salicide process).
Moreover, the thickness of the selectively grown silicon layer becomes thinner adjacent to the gate electrode. Accordingly, the shortest distance between the additional surface (where the metal is to be deposited) and the junction depth is determined at this portion. Thus, no matter how thick the selectively grown silicon layer is made at the other portions, its ability to block the leakage generation is not enhanced.
As described above, shrinkage of the MOSFET's dimensions requires commensurate shallowing of the source and drain junctions. At the same time, to secure high speed operation, silicidation of the source and drain regions is necessary. However, for silicidation of shallow junctions, the high-speed diffusion of metal atoms from the silicide induces substantial junction leakage current.
In order to suppress the leakage by an elevated source drain structure, it is necessary to increase the thickness of the selectively grown silicon layer nearly to the thickness of the gate electrode. However, formation of such a thick selective silicon layer of uniform thickness and uniform quality has been very difficult.